Browse Prior Art Database

Bipolar IGFET Memory Cell and Array

IP.com Disclosure Number: IPCOM000087741D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

De La Moneda, FH: AUTHOR

Abstract

A static memory cell is proposed which uses one bipolar and three insulated gate field-effect transistor (IGFET) devices. Power dissipation is less than that of conventional static six-device cells since one of its states is nonconducting.

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Bipolar IGFET Memory Cell and Array

A static memory cell is proposed which uses one bipolar and three insulated gate field-effect transistor (IGFET) devices. Power dissipation is less than that of conventional static six-device cells since one of its states is nonconducting.

A bipolar transistor and an IGFET are connected to form a circuit with two stable states which can be identified from its i(o) versus v(o) characteristic shown in Fig. 1A, along with the circuit schematic in Fig. 1b. The operation of this circuit is as follows: The base current drive of the bipolar 1 is controlled by the p- channel IGFET P(1). As v(o) increases, the IGFET is turned off, which diminishes the base current drive, while simultaneously the bipolar is driven out of saturation, and, consequently, its current gain increases. Since the effective current gain of the bipolar increases faster than the base current decreases, the output current i(o) increases towards its peak. The output current peaks when the bipolar is completely driven out of the saturation and its current gain is approximately constant and equal to the forward beta of the device. Further increases in v(o) continue decreasing the current of the p-channel device which, in turn, decreases the output current from its peak value and produces the negative resistance portion of the i(o) versus v(o) plot. For (v(o)- E(s)+ V(TP)) positive, the p-channel device is turned off and the output current vanishes.

A memory cell design...