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Computing Engine Without Branch Jump Instructions

IP.com Disclosure Number: IPCOM000087798D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Pinnell, MC: AUTHOR [+2]

Abstract

A conventional computing engine is able to execute conditional branch instructions consisting of the conditional branch operation code, the condition to be fulfilled, and the branch address, that is, the address of the next instruction to be fetched and executed if the condition is fulfilled. Since it is usually easier to write programs in a "go-to"-less block-structured form using IF, ELSE, WHILE statements, the compilers for conventional computing engines have to transform a "go-to"-less source program into an object program containing branch instructions, with semantic loss when debugging if not more generally.

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Computing Engine Without Branch Jump Instructions

A conventional computing engine is able to execute conditional branch instructions consisting of the conditional branch operation code, the condition to be fulfilled, and the branch address, that is, the address of the next instruction to be fetched and executed if the condition is fulfilled. Since it is usually easier to write programs in a "go-to"-less block-structured form using IF, ELSE, WHILE statements, the compilers for conventional computing engines have to transform a "go-to"-less source program into an object program containing branch instructions, with semantic loss when debugging if not more generally.

Fig. 1 shows part of a computing engine which interprets a source program exactly as it is written without the need to compile implicit "go-to" instructions and without needing to specify target instructions. Eight-bit cursor register 1, having a single-bit left or right shift, is connected to eight-bit trigger register 2 in such a manner that its contents can be exclusive-ORed bit by bit into trigger register 2. The output of trigger register 2 is received by zero detection logic 3. Whenever the contents of register 2 are zero, execution of the instruction in execution unit 4 is allowed; if the contents of register 2 are nonzero, execution unit 4 is disabled by condition trigger 5. Instructions are received in buffer 6 in the order in which they are written and are sequentially decoded in decoder 7.

Fig. 2 illustrates a typical block structured program. Instead of assembling conventional branch instructions with branch addresses, IF, ELSE and END IF statements are directly assembled as machine language instructions. Instructions are fetched and executed in unit 4 until an IF instruction is decoded by decoder 7. If the condition "A" is fulfilled, the immediately following instructions are fetched and executed until an ELSE instruction is received. At this stage, although the following instructions are fetched from buffer 6, their execution is disabled until the next END IF instruction is detected. If, on the other hand, condition "A" is not fulfilled, the...