Browse Prior Art Database

Fabrication Technique for Fully Recessed Oxide Isolation

IP.com Disclosure Number: IPCOM000087815D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 94K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

A technique for fabricating silicon dioxide regions for electrically isolating semiconductor devices in an integrated circuit has been described in U. S. Patent 3,899,363. The basic structure shown in Fig. 1 of this patent, consists of a thin layer of silicon dioxide (i.e., a padding layer) about 100 angstroms thick over which is deposited a thicker layer of silicon nitride about 2000 angstroms thick. Above that is another oxide layer used to define the nitride layer about 1500 angstroms thick used to define the nitride layer and to aid in ion-implantation blocking. In fabricating he recessed oxide regions the layered structure must block boron atoms from the device regions, minimize lateral oxidation effects, and not introduce strain damage into the device regions.

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Fabrication Technique for Fully Recessed Oxide Isolation

A technique for fabricating silicon dioxide regions for electrically isolating semiconductor devices in an integrated circuit has been described in U. S. Patent 3,899,363. The basic structure shown in Fig. 1 of this patent, consists of a thin layer of silicon dioxide (i.e., a padding layer) about 100 angstroms thick over which is deposited a thicker layer of silicon nitride about 2000 angstroms thick. Above that is another oxide layer used to define the nitride layer about 1500 angstroms thick used to define the nitride layer and to aid in ion- implantation blocking. In fabricating he recessed oxide regions the layered structure must block boron atoms from the device regions, minimize lateral oxidation effects, and not introduce strain damage into the device regions.

In practice one etches through the layers down to the silicon substrate and then uses an anisotropic etchant to produce a recess with a sloped sidewall. Using the upper oxide layer and the nitride layers together as an implantation blocking mask, boron ions are implanted into the exposed silicon substrate regions to provide a parasitic channel stopper beneath and beside (i.e., self- aligned to) the subsequently formed recessed oxide regions (Fig. 1A). After implanting the boron, the upper oxide layer is removed and the fully recessed oxide isolation grown by wet thermal oxidation (Fig. 1B).

Certain difficulties are associated with the process described above. First, the thick oxide over the nitride layer must be removed before growing the recessed oxide; otherwise, much of the recessed oxide would also be removed. Second, removal of the upper oxide layer undercuts the thin oxide padding layer and thus enhances lateral oxidation or "bird's beak" [1] during growth of the recessed oxide. If, in an attempt to simultaneously solve the two problems, one increases the nitride thickness and correspondingly decreases the thickness of the upper oxide, the thicker nitride layer can cause strain damage to the silicon substrate surface in the future device regions.

What is desired is an implantation blocking and oxidation barrier structure which:. 1. is thick enough to block the boron atoms during implantation, 2. does not cause undercutting of the oxide padding layer, 3. is retained during recessed oxide growth to prevent bending of the nitride and oxygen penetration of the nitride layer [2], 4. does not increase strain damage in the future device regions, and 5. uses well known materials common to integrated-circuit technology.

Disclosed here is a technique which satisfies the criteria listed above. The essential idea is to replace the thick oxide and nitride masking layers with a thick layer of polysilicon which is, in effect, surrounded by thin layers of nitride.

The new process is shown in Fig. 2. First, a thin oxide padding layer about 100 angstroms thick is grown by dry oxidation. Then a thin layer of silic...