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Josephson Device Latch With Output Gates

IP.com Disclosure Number: IPCOM000087832D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR [+2]

Abstract

A static flip-flop is disclosed which has "set", "reset" and "toggle" input and provides gated true and complement output signals compatible with latching logic. It comprises eight interferometers and can be accommodated in two unit cells.

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Josephson Device Latch With Output Gates

A static flip-flop is disclosed which has "set", "reset" and "toggle" input and provides gated true and complement output signals compatible with latching logic. It comprises eight interferometers and can be accommodated in two unit cells.

Fig. 1 shows a schematic of the circuit 1 which includes a DC powered superconducting loop 2 with a total of four Josephson gates J1-J4. Loop 2 controls two AND gates J5,J6 and J7,J8, with two inputs each and connected via a single feed resistor 3 to an AC power supply bus. Each of AND gates is connected to a pair of terminated transmission lines 4. The two AND gates occupy a unit cell adjacent to that accommodating the loop.

In operation, a set (reset) pulse directs the DC current through the branch of loop 2, with the reset (set) gate causing loop 2 to represent a binary 1 or 0. The toggle input differentiates the input pulse to a sufficiently short duration so as to accomplish the toggle action as follows: The toggle input switches Josephson gate J2, for example, through which the DC current is flowing, causing the DC current to be redirected into the other branch. The trigger pulse must be short enough so as not to remain effective while the loop current is being transferred through the gate which has not been switched.

The stored data in loop 2 is gated out at the beginning of the following AC power cycle by (a) activation of the latching double AND circuit and (b) the action of a g...