Browse Prior Art Database

Inclusion of Relatively Large Kinetic Inductances in Josephson NDRO Ring Cells

IP.com Disclosure Number: IPCOM000087837D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 23K

Publishing Venue

IBM

Related People

Henkels, WH: AUTHOR

Abstract

Projected speeds of Josephson memory chips are limited by the delays through necessary peripheral circuitry. The largest delays are associated with control and supply currents for the write gates of the memory cells. In general for unmatched Josephson circuits, the delay, deltat(i), associated with an i/th/ peripheral circuit is proportional to L(i), I(i) and V(i), i.e., (Image Omitted) where L(i), I(i), and V(i) are, respectively, the self inductance, current, and driving voltage of the i/th/ component. Thus, one straightforward means of decreasing memory chip cycle time is to decrease inductance levels, L(i), of the peripherals.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Inclusion of Relatively Large Kinetic Inductances in Josephson NDRO Ring Cells

Projected speeds of Josephson memory chips are limited by the delays through necessary peripheral circuitry. The largest delays are associated with control and supply currents for the write gates of the memory cells. In general for unmatched Josephson circuits, the delay, deltat(i), associated with an i/th/ peripheral circuit is proportional to L(i), I(i) and V(i), i.e.,

(Image Omitted)

where L(i), I(i), and V(i) are, respectively, the self inductance, current, and driving voltage of the i/th/ component. Thus, one straightforward means of decreasing memory chip cycle time is to decrease inductance levels, L(i), of the peripherals.

For a fixed line width (and layout), the only means of reducing the inductances of peripheral striplines is to reduce the insulation thicknesses, t(i), since the inductance per square is given by

(Image Omitted)

where lambda and d denote superconductive material penetration depth and thickness and the subscripts t and b denote top and bottom superconductors of the stripline. In equation (2), t (i)includes the thicknesses of any insulation common to and underlying the memory cell loops themselves. Hence, a straightforward reduction of all insulation layer thicknesses, in order to reduce peripheral inductances, also implies a reduction in the memory cell loop inductance.

Reduction of the memory cell loop inductance, L(?), results in the following disadvantages: (1) The critical damping resistance R(c) = square root of L(?)/4C (where C is the write gate capacitance) decreases and, as a result, makes damping via the internal junction single-particle resistance more difficult. (2) The static I(min) of the write gate increases, because I(min) approximates 1/R, wh...