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Verification of Engineering Changes

IP.com Disclosure Number: IPCOM000087863D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Roth, JP: AUTHOR

Abstract

The purpose of this procedure is to verify the correctness of Engineering Changes (ECs) to logical designs. The problem of verification of a design change is of universal character: the change is made for some specific purpose and yet it is required that other aspects of the design function not change. The algorithm given here ascertains for each output whether or not inadvertent changes in function were made.

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Verification of Engineering Changes

The purpose of this procedure is to verify the correctness of Engineering Changes (ECs) to logical designs. The problem of verification of a design change is of universal character: the change is made for some specific purpose and yet it is required that other aspects of the design function not change. The algorithm given here ascertains for each output whether or not inadvertent changes in function were made.

Assume that the original design, before the EC, is given as a list in the format of Regular Logic Design (RLD) [1], any list in a well defined logic design language. The list also contains a list of the Primary Inputs (FI) and Primary Outputs (PO) of the logic designs.

An EC then consists of a list of modifications to the original design in the form of ADDs and DELETEs to the list. In effect the EC defines, together with the original design, a new design, and it is the comparison of the consistency of these designs, at least in the parts that are not supposed to change, to which the present procedure is directed.

The D-algorithm was designed in terms of failures of individual circuits of a Logic Design. In this technique it is generalized to obtain tests for the validity of ECs. The principal modification made is in the computation of the primitive D- cubes for failure [2]. The individual circuit failure is replaced by the logic to be changed together with the logic into which it is changed.

Two methods for this purpose will be described. In the first the PISTAR procedure [3] is used. For every primary output of the logic to be changed (LC), the PISTAR algorithm is used to generate the ON and OFF arrays in terms of the primary inputs of...