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Family of Multiply Divide Instructions

IP.com Disclosure Number: IPCOM000087871D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Birney, RE: AUTHOR [+6]

Abstract

The data processing system features three types of multiply and divide based on a 16-bit computer format, and has increased efficiency in multiplying and dividing small integer numbers. The system includes a central processing unit (CPU) 1 with associated channel 1a, storage 2, and a device attachment 3 incorporating a microprocessor 4 for interconnection of a CRT display unit 5 having a keyboard 6 and display screen 9.

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Family of Multiply Divide Instructions

The data processing system features three types of multiply and divide based on a 16-bit computer format, and has increased efficiency in multiplying and dividing small integer numbers. The system includes a central processing unit (CPU) 1 with associated channel 1a, storage 2, and a device attachment 3 incorporating a microprocessor 4 for interconnection of a CRT display unit 5 having a keyboard 6 and display screen 9.

CPU 1 incorporates an arithmetic and logic unit (ALU) 10 with associated WA Register 11 and Y Register 12. See the article on pages 4062-4068 of this issue for more detailed discussion of these elements. A more comprehensive diagram is shown in Fig. 2. It includes a number of components more fully described in the above-mentioned article. Besides ALU 10, WA Register 11, and Y Register 12, it includes Counter 75, Storage Data Register 40, Op Register 35, and Stack
20.

The multiply algorithm is illustrated in Fig. 3.

Most machines using a 16-bit format, which offer hardware multiply/ divide instructions, only offer a single instruction for each. The typical facility (for example, the IBM 1800 System) allows 1 WD X 1 WD = 2 WD and 2 WD divided by 1 WD = 1 WD quotient, 1 WD remainder. Some of the disadvantages with such an approach are:.

1) Doubleword factors have to be contended with, even though the programmer knows that his data can never yield a double-word result.

2) When doubleword results are of interest, the divide instruction only supports a limited range of results. That is, the quotient must not be greater than 16 bits.

In the present system, the architecture has addressed this problem and offers both limited scope facility with the byte and word multiply/ divide, as well as an extended precision facility with the doubleword set. This is in contrast to the more classical facility which customarily does not offer such capability.

The byte multiply/divide for this system allows small integer factors (-128 to +127) to be represented as a byte (R bits) in storage. The supported formats are: Byte (storage) X word (register) = word (register) Word (register) divided by byte (storage) = word quotient (register), word remainder (regist...