Browse Prior Art Database

Class Interrupt Status Save

IP.com Disclosure Number: IPCOM000087977D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 5 page(s) / 49K

Publishing Venue

IBM

Related People

Birney, RE: AUTHOR [+3]

Abstract

The system features elimination of software save of machine status and initialization of new supervisor status on class interrupt actions.

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Class Interrupt Status Save

The system features elimination of software save of machine status and initialization of new supervisor status on class interrupt actions.

A representative system, Fig. 1, includes a central processing unit (CPU) 1 with associated channel 1a, storage 2, and a device attachment 3 incorporating a microprocessor 4 for interconnection of a CRT display unit 5 having a keyboard 6 and display screen 9, or other input/output device.

In another article on pages 4062-4068 of this issue, various components of the representative CPU 1 are shown in the drawings and described in more detail. These include a Processor Status Word (PSW) Register 55 and Level Status Block (LSB). See Figs. 2 and 3 of that article.

In a system of this nature which uses priority interrupts to cause prioritized program execution, it is desirable to provide for certain error, exception, and supervisor request transitions to occur on a given priority interrupt level with minimum impact to other (higher) priority interrupt levels. Furthermore, it is desirable to cause these transitions to occur such that the state of the machine prior to the transition is completely saved, and all facilities are immediately available to the program running in the new state. It should further be noted that it is desirable to effect the above without change of operational priority level. The present version provides a group of "class" interrupts and a status saving and restoring mechanism for operation in a single or multiaddress space system.

A number of "class" interrupts are defined corresponding to desired transitions. Examples are:
SVC Supervisor Call Supervisor Request Transition SEXP Soft Exception Emulation-Resource Manager Transition PCK Program Check Programming Error Manager Transition MCK Machine Check Hardware Error Manager Transition TRA Trace Instruction Trace Manager Transition CON Console Console Interface Manager Transition PTW Power Thermal Warning Machine Failure Manager Transition

A "Processor Status Word" (PSW) is defined to allow definition and recording of multiple causes for some or all of the defined transitions. An example is shown in Fig. 2.

PSW Bit Definitions are: Type Bit Cause 0 Specification Check

1 Invalid Storage Address

Program Check 2 Privilege Violate 3 Protect Check

4 Invalid Function (Either

Program check

or soft exception trap)

5 Floating Point Exception

Soft Exception Trap 6 Stack Exception

1

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7 Reserved

8 Storage Parity Check

9 Reserved

Machine Check 10 CPU Control Check 11 I/O Check

12 Sequence Indicator

Status Flags 13 Auto IPL 14 Translator Enabled

Power/Thermal 15 Power/Thermal Warning

A storage address pair is defined for each class interrupt. One address specifies the location in storage for program execution to begin as a result of the occurrence of the defined transition. The address specifies the location in storage where the machine status is to be stored during the transition process. The storage ad...