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Save Storage Address on Error Class Interrupts

IP.com Disclosure Number: IPCOM000087979D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 6 page(s) / 147K

Publishing Venue

IBM

Related People

Birney, RE: AUTHOR [+2]

Abstract

The data processing system features software error correction or retry for machine error conditions and saves the contents of a Level Status Block, a Storage Address Register and its corresponding Address Space Key for error recovery. The system includes a central processing unit (CPU) 1 with associated channel 2, storage 3, and a device attachment 4 incorporating a microprocessor 5 for the interconnection of a CRT display unit 6 having a keyboard 7 and display screen 8. Other input/ output devices such as device 9 are also accommodated. CPU 1 has a console 10 attached.

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Save Storage Address on Error Class Interrupts

The data processing system features software error correction or retry for machine error conditions and saves the contents of a Level Status Block, a Storage Address Register and its corresponding Address Space Key for error recovery. The system includes a central processing unit (CPU) 1 with associated channel 2, storage 3, and a device attachment 4 incorporating a microprocessor 5 for the interconnection of a CRT display unit 6 having a keyboard 7 and display screen 8. Other input/ output devices such as device 9 are also accommodated. CPU 1 has a console 10 attached.

The CPU 1 includes an Arithmetic and Logic Unit (ALU) 11. A pair of input registers WA 12 and Y 13 are provided for input to ALU 11. ALU 11 is a 16-bit unit which performs arithmetic and logical functions as specified by the instructions. The WA register 12 is a 16-bit register which is the primary input to ALU 11 for arithmetic and logic operations. The Y register 13 is a 16-bit register which is the secondary input to the ALU 11 for arithmetic and logic operations. ALU 11 has an output coupled to processor bus 17 (Fig. 2A). Processor bus 17 in turn is coupled to registers 12 and 13 by way of AND gates 15 and 16, respectively, to provide input data to ALU 11.

Processor bus 17 acts as the main data bus for both source and destination data. Most of the functional components of the system act as both a source and a destination for data, and, therefore, are coupled to processor bus 17 by both source AND gates and destination AND gates.

The Local Storage Register Stack 20 (Fig. 2B) contains the registers that make up the four Level Status Blocks (LSB), Console Data Buffer, Stop-On- Address Buffer, Address Keys and Instruction Address for each of the four interrupt levels, and other registers used by the microprogram during processing. Stack 20 is further illustrated in detail in Fig. 3. Stack 20 is accessed by Stack Address Register 45. It also contains certain other working registers used by the microprogram, i.e., the TEMP, TEMP1-3, DBUF, SOA1, SOA2, Current Level Save and AKR Save. The TEMP and TEMP1-3 registers contain temporary data used by the microprogram during normal processing. SOA1 contains the manually entered address to be used for stop-on-address operations, and SOA2 contains the console storage key in the low three bits, the remaining bits being zero. The DBUF register is the console 10 data buffer. The contents of this buffer drives data display indicators (not shown) on the console 10. The Current Level Save register contains the level that was active when the stop state was entered. The AKR Save register contains a copy of the current level AKR. The data in the AKR, LSR and IAR registers of stack 20 for the current level are also held in the corresponding hardware registers 25, 30, 47 for performance reasons,
i.e., to reduce the number of stack accesses.

The Hardware Level Status Register (LSR) 30 is a 16...