Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Density Silicon Gate Field Effect Transistor Fabrication Process

IP.com Disclosure Number: IPCOM000087994D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Adler, E: AUTHOR

Abstract

This article describes a process for fabricating a high density silicon gate field-effect transistor (FET) having low parasitic capacitance for use as memory or logic. The described process particularly produces an FET which uses diffusion store at one level polysilicon with a silicon gate.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

High Density Silicon Gate Field Effect Transistor Fabrication Process

This article describes a process for fabricating a high density silicon gate field-effect transistor (FET) having low parasitic capacitance for use as memory or logic. The described process particularly produces an FET which uses diffusion store at one level polysilicon with a silicon gate.

The specific sequence of steps to produce the structure is as follows: A substrate 10 formed of boron-doped single crystal silicon is oriented, cut, lapped, etc., and coated with a 2,500 angstrom-thick layer of arsenic-doped oxide 11, formed by any convenient technique and coated with a chemical-vapor-deposited layer of silicon dioxide 12 which is also 2,500 angstroms thick. Once the layers have been formed, they are delineated into specific regions 13, 14 and 15 using well known photolithographic techniques. Once the regions are delineated, the wafer is heated to a temperature of approximately 900 degrees to 1,000 degrees C, and the arsenic and oxide layer 11 is diffused into the semiconductor body to form diffusions 16, 17 and 18. Following this diffusion step, the channel region between diffusions 16 and 17 is ion-implanted with boron ions to a density of 10/19/ atoms per cm/3/ to compensate for any undesired arsenic diffusion therein and to assure suitable future gate control. Following this ion-implantation step, the regions 13 and 15 are again masked in the conventional manner, and the oxide region 14 as well as the surrounding layers 19 of silicon dioxide are removed by using a suitable etch which attacks the silicon dioxide layers.

Following the removal of the layer 14 and the layer 19, a thin gate oxide 20 (Fig. 2) is formed over the surface of the semiconductor body, utilizing the well- known dry thermal technique, and grown to a thickness of between 450 and 500 angstroms. If desired, this gate oxide 20 can be grown in a hydrochloric acid environment to improve the quality of the oxide layer 20. Following this creation of the layer 20, a uniformly thick polysilicon layer 21 on the order of 5,000 angstroms in thickness is formed over the...