Browse Prior Art Database

Merged Surface Charge Gated Junction FET Memory

IP.com Disclosure Number: IPCOM000087998D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Lee, HS: AUTHOR

Abstract

A current-sensing merged charge memory is provided which has high density and high performance. Information is stored in potential wells of a semiconductor substrate 10 with junction field-effect transistor (FET) sensing techniques employed to sense the stored information nondestructively.

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Merged Surface Charge Gated Junction FET Memory

A current-sensing merged charge memory is provided which has high density and high performance. Information is stored in potential wells of a semiconductor substrate 10 with junction field-effect transistor (FET) sensing techniques employed to sense the stored information nondestructively.

In the figures, the memory is shown with the semiconductor substrate 10 of N-type material having a pocket 12 of P-type material forming a P-N junction 14. Edge 16 defines the P-N junction depletion region in the P-type pocket 12 and edge 18 defines the P-N junction depletion region in the N-type material 10. A plurality of lines 20, 22, 24 and 26, preferably made of polysilicon, form bit lines for writing information into the memory. These bit lines are arranged parallel to each other and are insulated from the surface of substrate 10 by a thin layer of insulation 28, preferably silicon dioxide. Charge sources 30 and 32 are formed as N+ strips within the P-type pocket 12 and are arranged parallel to the bit lines. A word line 34, extending between charge sources 30 and 32, overlies the bit lines which are separated from the word line 34 by insulating layers 36, 38, 40 and 42. A pair of read select terminals are provided in ohmic contact with and at opposite ends of the P-type pocket 12, with read select source RSs being located near charge source 30 and read select drain RSd positioned near charge source
32.

As shown in Fig. 2, which is a section taken through line 2-2 of Fig. 1, the P- type pocket 12 is isolated from other portions of substrate 10 by recessed oxide walls 44 and 46 as well as by the P-N junction 14. When deep P-type pocket isolation is desired, N+ regions 48 and 50 may be disposed underneath the recessed oxide walls 44 and 46, as indicated in Fig. 2A, which is a section corresponding to that illustrated in Fig. 2.

In the operation of the memory, to write information, a voltage of, e.g., 8.5 volts, is applied to one of the bit lines 20, 22, 24 or 26 to store a 0 bit of information and 4.5 volts is applied to one of the bit lines to store a 1 bit of information, forming depletion wells 52 in the P-type pocket 12. With the 8.5 or
4.5 volts on the bit lines, a voltage of 4.5 volts is applied to word line 34 to produce inversion layers at the surface of substrate 12, which interconnects serially the depletion wells 50 to the charge sources 30 and 32. The charge sources are pulsed so that charges fill the potential wells created by the 8.5-volt bit line potential until they are half full, with the potential wells created by the 4.5- volt bit line potentials receiving little, if any,...