Browse Prior Art Database

Proportional Variable Time Delay Stepping Motor Control System

IP.com Disclosure Number: IPCOM000088007D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Bolcavage, RD: AUTHOR [+3]

Abstract

This control system continuously varies the phase relationship between the feedback signals from emitter 19 and the next motor advance signal from the time delay compare (TDC) 14. This relationship controls the average force exerted by the motor 18, thus controlling its speed.

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Proportional Variable Time Delay Stepping Motor Control System

This control system continuously varies the phase relationship between the feedback signals from emitter 19 and the next motor advance signal from the time delay compare (TDC) 14. This relationship controls the average force exerted by the motor 18, thus controlling its speed.

Velocity measurement counter (VMC) 10 provides two functions. It supplies a timing reference to be used to generate motor advances with the proper phase relationship to the feedback signals, and it also continuously measures motor velocity, thus supplying information to be used to modify the time delay register (TDR) 12.

The full adder 11 is used to add the residual count in VMC 10 to the value of TDR 12 and to update the TDR 12. The TDR 12 stores the new time delay for comparison with the count of VMC 10 by TDC 14 to generate motor advance pulses.

The gate control logic 13 controls how often the TDR 12 is updated. This prevents the motor from excessive hunting about an average velocity. Gate control 13 also prevents modifying the delay while the pedestal control 15 is active.

The pedestal control 15 supplies extra power to motor 18 when accelerating or stopping the motor. The stop control 15a modifies the motor advance to supply negative force when stopping motor 18.

The motor sequence control 16 provides the proper energization sequences for the windings of motor 18 connected to be energized by motor drivers 17.

Initially a nominal time delay is set in TDR 12. This delay is used until motor 18 has accelerated up to speed. The initial advance pulse applied to motor sequence logic 16 causes the motor to accelerate to the first feedback. Once the motor has accelerated to the desired velocity, gate control 13 allows a number of events to take place as a result of the first feedback pulse. (1) The adder 11 takes the residual count in the VMC 10...