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Isolation Process for Shallow Junction Devices

IP.com Disclosure Number: IPCOM000088038D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+2]

Abstract

When boron is used to isolate NPN transistors, it diffuses laterally as much as vertically. This requires a large base-to-isolation spacing to avoid base-isolation shorts, thereby reducing the circuit density for a given chip size.

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Isolation Process for Shallow Junction Devices

When boron is used to isolate NPN transistors, it diffuses laterally as much as vertically. This requires a large base-to-isolation spacing to avoid base- isolation shorts, thereby reducing the circuit density for a given chip size.

A solution to this problem is to cause preferential vertical diffusion as compared to lateral diffusion. As shown in the figure, the areas used for isolation are opened and predamaged with /+/Si/28/ at an approximate dosage of 1 x 10/15//cm/2/. This results in the conversion of these regions to the amorphous state. Boron is then diffused. Because the diffusivity of boron in the amorphous silicon is much higher than in crystalline silicon, the lateral diffusion of boron will be practically zero.

The predamaged silicon may also be oxidized if dielectric isolation is desired.

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