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Self Contained Bipolar FET Device

IP.com Disclosure Number: IPCOM000088049D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Carballo, RA: AUTHOR [+2]

Abstract

A bipolar device having emitter, base and collector contacts 10, 12, 14, respectively, is self-coupled with high impedance P channel field-effect devices having source, base-drain and gate contacts 18, 20, 22, respectively, around the periphery of the base of the bipolar device is shown in Figs. 1 and 2. Fig. 3 shows the circuit of the Figs. 1 and 2 device structure. The source of MOSFETs (metal-oxide semiconductor field-effect transistors) regions are directly coupled to the base, converting a bipolar low impedance to a high input impedance circuit using an added gate or for biasing purposes.

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Self Contained Bipolar FET Device

A bipolar device having emitter, base and collector contacts 10, 12, 14, respectively, is self-coupled with high impedance P channel field-effect devices having source, base-drain and gate contacts 18, 20, 22, respectively, around the periphery of the base of the bipolar device is shown in Figs. 1 and 2. Fig. 3 shows the circuit of the Figs. 1 and 2 device structure. The source of MOSFETs (metal-oxide semiconductor field-effect transistors) regions are directly coupled to the base, converting a bipolar low impedance to a high input impedance circuit using an added gate or for biasing purposes.

The MOSFETs are formed on the skirt of the base by selectively diffusing P type impurities in the collector region when the base of the transistor is formed. The FET (field-effect transistor) devices have a common drain which is the base of an NPN transistor, and the sources are the P regions in the collector region. The gates of the P channel FETs can be formed by either of two methods: (a) selectively etching the Sin over the gate region to a proper gate oxide thickness, and (b) removing the SiO(2) in the gate region and region SiO(2) to gate silicon dioxide thickness.

The structure is isolated from other parts of the integrated circuit by junction isolation region 24 or by recessed junction oxide isolation. The FET substrate bias (negative) is common to the collector by typical NPN configuration. The FETs are thereby combined with bipola...