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Circuit Presenting a High Input Impedance

IP.com Disclosure Number: IPCOM000088061D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Delarue, G: AUTHOR [+3]

Abstract

The drawing shows a high input impedance circuit incorporated in a sample-and-hold device for preventing the holding capacitor from discharging during the hold status.

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Circuit Presenting a High Input Impedance

The drawing shows a high input impedance circuit incorporated in a sample- and-hold device for preventing the holding capacitor from discharging during the hold status.

Sample-and-hold devices comprise a switching circuit controlled through sampling pulses, connected to a buffering operational amplifier and a holding capacitor connected to the input I of the buffering amplifier. Only the buffering amplifier and the high input impedance circuit are represented.

The high impedance circuit comprises a current compensation network for generating, at node I, current i2 which is equal to input current of the buffering amplifier in order to cancel current i3 in the input branch. Thus, the impedance of this network is very high.

The buffering amplifier is composed of transistors T1 to T8 with biasing diodes D1 to D7. The compensation network comprises two transistors T9 and T10 which are matched with transistors T1 and T2 and a current mirror M. Current mirror M provides two equal currents i in the collector paths of transistors T10 and T2.

Transistors T1 and T9 are supplied with the same collector voltage. Collector voltages of transistors T2 and T10 are nearly equal. Consequently, arrangements of transistors T9 and T10 and of transistors T1 and T2 are balanced, which makes current i2 equal to i1, and input current i3 at node I tends towards zero.

Residual current Delta i3 mainly depends on Beta matching of transistors T1 and T9...