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Recorder for Control Program Sequences

IP.com Disclosure Number: IPCOM000088063D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hajdu, J: AUTHOR [+2]

Abstract

Previous recorders for control program sequences have the drawback that their capacity is very rapidly exhausted during the execution of program loops and that older program parts once overwritten by new ones can no longer be referred to.

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Recorder for Control Program Sequences

Previous recorders for control program sequences have the drawback that their capacity is very rapidly exhausted during the execution of program loops and that older program parts once overwritten by new ones can no longer be referred to.

This problem can be solved by the use of an associative address back-up store which is operated in such a manner that used addresses, when they are re- encountered, for example, the next time a loop is retaken, occupy the same storage position, and that subsequently the next address is referred to.

The addresses transferred from control store address register (CSAR) to the control store (CS) are fed to the associative address back-up store. Each address position of the latter store comprises a register and a comparer. The associative address back-up store is addressed via an address register ADDR REG at the beginning of the operation, starting with address 0. The first microinstruction address appearing on the output of CSAR is thus fed to the storage area associated with address 0 in the associative address back-up store.

As at the beginning of recording, there is no instruction address in this storage area, the compare operation of the comparer associated with this area will indicate that the register contains no identical address information, so that via the "no match" line a corresponding output signal is applied for the address control of the associative back-up store. This signal causes the address to be modified by +1, modifier MOD to be fed via AND gate G1 and the connected OR gate to address register ADDR REG, thus addre...