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Merged Transistor Logic Layout

IP.com Disclosure Number: IPCOM000088067D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+3]

Abstract

The basis for the layout is the structure of the merged transistor logic (MTL) shown in Fig. 1. This basic structure consists of an upside-down operated vertical transistor structure forming an inverter and comprising one or several collector zones N2 in a base zone P2 lying in an emitter zone N1. The transistor structure, controlled on the contact to base zone P2, is fed with operating current via an injection zone P1, arranged in the proximity of the base-emitter junction in emitter zone N1 and to which current I is applied. Collector zones N2 form the outputs of the multicollector inverter.

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Merged Transistor Logic Layout

The basis for the layout is the structure of the merged transistor logic (MTL) shown in Fig. 1. This basic structure consists of an upside-down operated vertical transistor structure forming an inverter and comprising one or several collector zones N2 in a base zone P2 lying in an emitter zone N1. The transistor structure, controlled on the contact to base zone P2, is fed with operating current via an injection zone P1, arranged in the proximity of the base-emitter junction in emitter zone N1 and to which current I is applied. Collector zones N2 form the outputs of the multicollector inverter.

Such multicollector inverters are the basic building blocks for MTL logic. By dotting the collector outputs of different inverters, the logic function is realized.

Fig. 2. shows an example of the layout of a logic block with three input signals A, B, C and output signals A B, (A + B) C, A C. For this logic function several stripe-shaped base zones P2 are arranged in parallel in the common emitter zone N1. Perpendicular thereto, wiring channels (5 in the example) are defined which, according to the logic function required, are connected to collector zones N2 or base zones P2 via contacts c, or which pass the base zones without contacts.

As a rule, injection zones P1 are arranged on both sides of base zones P2, so that the operating current is applied to base zones P1 from both sides, and series resistance problems are avoided.

The example of Fig. 2 shows that the utilization of stripe-shaped base zones P2 is not an optimum one, since many of the positions defined by the wiring channels remain empty. This leads to losses with rega...