Browse Prior Art Database

FET Structures with High Resistivity Substrates

IP.com Disclosure Number: IPCOM000088075D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Kotecha, HN: AUTHOR [+2]

Abstract

A process and structure are disclosed for a field-effect transistor (FET) device which has depleted regions under its channel that are less likely to merge, thereby improving the short channel and punch-through characteristics thereof.

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FET Structures with High Resistivity Substrates

A process and structure are disclosed for a field-effect transistor (FET) device which has depleted regions under its channel that are less likely to merge, thereby improving the short channel and punch-through characteristics thereof.

The figure shows a semiconductor structure for an FET device wherein the source region 2 and drain region 3 are formed in the substrate 1 of a first conductivity type, by preferentially etching V-grooves 4 and 5, respectively, in the substrate 1. This is followed by forming the junction for the source and drain either by ion-implantation or by diffusion of a dopant of a second conductivity type into each of the grooves 4 and 5. The junctions thus formed taper away from each other so that the associated depletion regions under the channel 6 are less likely to merge, thereby improving the short channel and punch-through characteristics of the device. The device is completed by growing a thin oxide gate insulator layer 7 and a thick oxide field insulator layer 8 followed by the deposition of the source and drain metallurgical contacts 9 and 10 and the gate electrode 11.

The process for forming this structure includes the use of an anisotropic etchant for etching the V-shaped grooves 4 and 5 in the semiconductor substrate
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