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Random Delay Simulation

IP.com Disclosure Number: IPCOM000088080D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Savkar, AD: AUTHOR

Abstract

Existing computer programs for extreme delay simulation of logic circuits include routines for simulating variances in circuit delays resulting from, among other things, an imperfect manufacturing process. In existing extreme delay simulation, a minimum delay, i.e., when a circuit does not start switching prior to this time, and a maximum delay, i.e., when the circuit switch is complete and certain after this time, are specified and both delay points are simulated. This mode of simulation is time consuming and the period of uncertainty between the minimum and maximum points propagates as time advances, often rendering useless the results of the simulation of a design with many memory elements.

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Random Delay Simulation

Existing computer programs for extreme delay simulation of logic circuits include routines for simulating variances in circuit delays resulting from, among other things, an imperfect manufacturing process. In existing extreme delay simulation, a minimum delay, i.e., when a circuit does not start switching prior to this time, and a maximum delay, i.e., when the circuit switch is complete and certain after this time, are specified and both delay points are simulated. This mode of simulation is time consuming and the period of uncertainty between the minimum and maximum points propagates as time advances, often rendering useless the results of the simulation of a design with many memory elements. Nominal delay simulation is good for functional verification and is cheaper to run, but nominal delay simulation does not simulate the delay variances, and hence a designer cannot depend on this mode of simulation alone.

This article describes a method and implementation for a new simulation algorithm which is called "random delay simulation". In this mode, assuming a normal distribution of delays for purposes of discussion, the delay spread is divided into N equal segments (see figure). Each circuit will have its minimum and maximum and its corresponding N divisions, keeping N the same for all circuits, for convenience. Using a random number generator, a random integer is generated between 1 and N for each circuit. The delay corresponding to this ra...