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Power Transistor Transient Life Test

IP.com Disclosure Number: IPCOM000088086D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Hathaway, JW: AUTHOR [+2]

Abstract

The system accelerates the aging of power transistors by stressing them in a transient mode. With this apparatus, a predetermined number of turn-off pulses can be applied to the base of any one of 10 transistors.

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Power Transistor Transient Life Test

The system accelerates the aging of power transistors by stressing them in a transient mode. With this apparatus, a predetermined number of turn-off pulses can be applied to the base of any one of 10 transistors.

The stress pulse is derived by gating the output of a single-shot variable width pulse generator to a gated pulse generator which is connected, through a switch S, to the base of one of 10 transistors that is monitored for second breakdown (SB-1 through SB-10).

Associated with each of the transistors to be tested is a protect circuit which, when its associated transistor goes into second breakdown, will, through another switch S, cause the setting of a latch which will inhibit subsequent pulses from the gated pulse generator. When this occurs, the counter that is connected to the output of the gated pulse generator will contain an indication of the number of pulses that had been applied to the base of the transistor prior to the second breakdown.

The sequencing of the 10 transistors under stress can be performed manually or automatically.

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