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Complementing Logic Functions that have Mutually Exclusive Controls

IP.com Disclosure Number: IPCOM000088090D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 70K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

Many logic functions arise that consist of selecting a number of data or conditions by means of a mutually-exclusive set of control signals. In some cases it is desirable to generate a particular polarity, true or complement, instead of the polarity resulting from expressing the function in easily understandable form, such as AND-OR.

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Complementing Logic Functions that have Mutually Exclusive Controls

Many logic functions arise that consist of selecting a number of data or conditions by means of a mutually-exclusive set of control signals. In some cases it is desirable to generate a particular polarity, true or complement, instead of the polarity resulting from expressing the function in easily understandable form, such as AND-OR.

Contemporary logic is inherently inverting logic, such as the NAND/AND-DOT logic. The logic corresponds to AND-OR-INVERT logic. Present technology also uses off-chip driver circuits (SENDS) which may be used as the OR, both as a 2- input OR as well as a DOT-OR of 2 or more SEND circuits, depending on circuit rules. be used as the OR, both as a 2-input OR as well as a DOT-OR or more SEND circuits, depending on circuit rules.

To derive the desired polarity output signal and still implement to use 2 gate levels of logic. To generate the positive polarity function when the controls are available at the input in positive form, 2 gate levels are used, the NAND/DOT- AND level and an inverter to change the AND-OR-INVERT into an AND-OR.

When expanded to a function of more terms than the AND-DOT can handle, the groups of terms form a bundle of signals into the second level gate. The function can be expanded to still more terms so as to use the maximum size bundle of signals entering the second level. Beyond that, two or more second- level gates can be ORed using SEND circuits.

This article describes a technique which generates the desired polarity of the function in one gate level. Using these methods, the size of the function that can be generated in 2 levels can also increase.

Figs. 1a through 1c illustrate methods of generating the 5-term function F in one level. Fig. la assumes that the 5 control signals (C1-C5) are not only mutually-exclusive but that exactly one of them must be on at any one time. In other words, they cannot all be off. In this case, the positive polarity function F is generated in one gate level simply by entering the data factors D1 through D5 in complemented form.

Fig. 1b assumes that the control signals may all be off. The function can now be implemented by augmenting the logic with the additional gate and signal, (C1.....C5).

An alternative to Fig. 1b, which eliminates the need for an extra gate, is to incorporate (C1,...,C5) with all inputs in any one of the 5 gates. For example, in Fig. 1c, the first-gate includes (C1,...,C5+D1) as we...