Browse Prior Art Database

Testable Checkers for Decoders

IP.com Disclosure Number: IPCOM000088095D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 5 page(s) / 157K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

When a decoder and its checker are located on the same chip, additional chip inputs are needed to make the decoder checker fully testable. Two methods, to be described, make a decoder checker fully testable. They apply to decoder checkers where the function is called a multiple selection detector.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 80% of the total text.

Page 1 of 5

Testable Checkers for Decoders

When a decoder and its checker are located on the same chip, additional chip inputs are needed to make the decoder checker fully testable. Two methods, to be described, make a decoder checker fully testable. They apply to decoder checkers where the function is called a multiple selection detector.

A first method is illustrated in Fig. 1. Five test inputs are used. One (A) enters one of the decoder gates (any gate will do) to enable all decode outputs to become inactive. The next 3 test inputs (B, C, and D) each control in true/complement fashion a corresponding pair of AND-DOTted gates. This assures a single path through the checker for all test conditions. The last test input (E) deactivates the complement gates of the B, C, and D test inputs to enable all 6 checker control lines to be up for normal operation.

Fig. 2 illustrates a second method, in which only 3 test inputs are needed at the expense of added gates. The test inputs are decoded to provide the 7 control lines of the first method, but only one is active at a time. The test input condition A B C is not generated and enables the checker to operate normally, while all 7 control lines are inactive (UP).

If a decoder does not use the full set of decoder outputs, the checker can be simplified and no external stimulation is needed to force all available decoder outputs inactive. Figs. 3 and 4 show a 4-bit decoder with only 7 of 16 outputs used and with a corresponding decoder...