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Timing Test for Dynamic Shift Register

IP.com Disclosure Number: IPCOM000088096D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Thorpe, WR: AUTHOR

Abstract

Circuits that are abnormally sluggish or sensitive represent potential reliability problems. The timing of each stage of a dynamic shift register (DSR) can be checked with the technique described below.

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Timing Test for Dynamic Shift Register

Circuits that are abnormally sluggish or sensitive represent potential reliability problems. The timing of each stage of a dynamic shift register (DSR) can be checked with the technique described below.

The drawing shows one stage of an FET (field-effect transistor) DSR. In normal operation, negative clock pulses A and B, which do not overlap in time, are used to cause a bit to shift from the input (which is the output of the previous stage) to the output (which is the input to the next stage).

For this timing test, the clock A and B pulses are overlapped as shown. After A goes positive, B remains negative for an amount of time t. While A and B are both at -V, all devices are on and all metallurgy and diffusions are at -V. When A goes positive, nodes 1 and 2 go positive. Then B goes positive, fixing the positive charge at node 2.

Varying the time t will control the amount of positive charge that is available when B goes positive. For the DSR stages, there is a range of values of t that correspond to acceptable amounts of charge at which node 2 will hold its positive charge when B goes positive. There is an upper bound t(max) for which any good stage should be able to shift data from input to output. There is also a lower bound t(min) for which any good stage should not shift.

To test for sluggishness, clocks A and B are applied to all DSR stages with t = t(max). After B goes positive, each stage should contain 1. The stages...