Browse Prior Art Database

Symmetrical Odd Integer Divider Circuit

IP.com Disclosure Number: IPCOM000088097D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kahwaty, VN: AUTHOR [+2]

Abstract

Many conventional divide-by-an-odd-number divider or counter produces an asymmetrical output from symmetrical inputs. In many applications, however, the asymmetrical output produces undesirable harmonics that need to be filtered. A symmetrical output is desirable because it does not produce such harmonics and the resultant filter is simplified. Shown in Fig. 1 is a schematic diagram showin; how any nonsymmetrical divide-by-odd-integer circuit can be connected to provide a symmetrical output, and shown in Fig. 3 is the specific application to a divide-by-three circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Symmetrical Odd Integer Divider Circuit

Many conventional divide-by-an-odd-number divider or counter produces an asymmetrical output from symmetrical inputs. In many applications, however, the asymmetrical output produces undesirable harmonics that need to be filtered. A symmetrical output is desirable because it does not produce such harmonics and the resultant filter is simplified. Shown in Fig. 1 is a schematic diagram showin; how any nonsymmetrical divide-by-odd-integer circuit can be connected to provide a symmetrical output, and shown in Fig. 3 is the specific application to a divide-by-three circuit.

With reference to Fig. 1, a waveform having a symmetrical input frequency F is fed to the input of a divide-by-an-odd-integer N circuit 2 which produces on output line 4 a signal having an asymmetrical waveform. This waveform is applied to the input of a logic circuit 6 having an output connected to the preset input PR of a D-type flip-flop (FF) 8. Circuit 6 produces the connect preset signal for operation of FF 8 by combinational logic. The input waveform is also fed by line 10 to the clock input CL of FF 8. The D input is grounded. The shorter half of the asymmetrical waveform is used to condition FF A whereby the next leading edge of the input waveform applied to the input CL actuates or switches FF 8.

The principle upon which the circuit is based is that when an odd divisor is applied to a symmetrical pulse train, the following output waveform symmetry is ...