Browse Prior Art Database

Primary Power Phase Monitor

IP.com Disclosure Number: IPCOM000088100D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Williams, KR: AUTHOR

Abstract

The primary power phase monitor circuit is used to detect primary power phase reversal and to transmit that information to a power controller. The input to the circuit is a three-phase power line, and the outputs are completely isolated from the input power line.

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Primary Power Phase Monitor

The primary power phase monitor circuit is used to detect primary power phase reversal and to transmit that information to a power controller. The input to the circuit is a three-phase power line, and the outputs are completely isolated from the input power line.

The inputs to the flip-flop 10 correspond to the signals on the respective lines,
i.e., when phase A is above ground, the clock input CK is high. Thus, if phase B is below ground when phase A crosses from negative to positive a zero will be clocked into the flip-flop at D. This indicates a proper phase sequence because phase 3 lags phase A by 120 Degrees and will be negative during this time. However, if B and C are reversed (or any other combination), a 1 will be clocked into the flip-flop at D due to the fact that C leads A by 120 Degrees and is positive when A crosses from negative to positive.

When phase A passes from negative to positive, optical isolator photodiode D3 conducts, turning on optical isolator phototransistor Q1 such that the negative terminal of comparator 12 is at ground potential. The positive terminal of comparator 12 is at some positive potential determined by resistors R11, R15 and the +5 V supply. Accordingly, comparator 12 produces a high or up-level output to the flip-flop 10. If the phase relationship of phase B with respect to phase A is correct, phase B should be negative when phase A is positive. Accordingly, photodiode D4 is not conducting; ther...