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Internal Oscillator Ring

IP.com Disclosure Number: IPCOM000088114D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Heuer, DA: AUTHOR [+3]

Abstract

With the advent of large scale integration (LSI) technologies, an increased quantity of logic may be packaged at the first level package. When the logic package is manufactured, it must be tested, and when logic is sequential in nature, the testing problem is increased. It is, in addition, more difficult to provide realistic delay measurement tests and testers. Therefore, present tests tend to be strictly DC, i.e., one input pattern is applied and sufficient time is allowed for all outputs to reach a steady-state before the output states are measured.

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Internal Oscillator Ring

With the advent of large scale integration (LSI) technologies, an increased quantity of logic may be packaged at the first level package. When the logic package is manufactured, it must be tested, and when logic is sequential in nature, the testing problem is increased. It is, in addition, more difficult to provide realistic delay measurement tests and testers. Therefore, present tests tend to be strictly DC, i.e., one input pattern is applied and sufficient time is allowed for all outputs to reach a steady-state before the output states are measured.

A reduction in the number of test patterns required to provide satisfactory test results, as well as an improvement over conventional DC testing, can be obtained by including an internal inverter ring (Fig. 1). This ring is constructed using an odd number of inverting circuits. The signal levels and waveforms shown in Fig. 1 are for NOR logic blocks. However, the technique may be applied to NAND logic as well.

An output -Osc may be obtained from the ring by either of two modes of operation. In a first mode, with + Inhibit Osc Ring at an up level an external oscillator + Ext Osc, may be switched by individual pattern inputs 1-5 with the resultant -Osc inverted from the input and delayed by one circuit. In a second mode, when the + Ext Osc is inactive and the input + Inhibit Osc Ring is switched to the down level at 6, a wavefront propagates through the ring causing the output -Osc to switch, as shown. The duration of the up and down time of the output is equal to the delays of the circuits in the ring.

The logic chip in which the inverter ring was used is a microprocessor unit (MPU) controlled by a three-phase clock ring. Thus, for a clock cycle of three clock times, 18 transitions on -Osc are required, as shown in Fig. 2. These may be obtained from 18 input transitions on + Ext Osc or from the free-running inverter ring.

Three additional elements are included in the oscillator ring used In the MPU of the example: a Power On Reset, a test point to facilitate DC stuck fault testing of the ring itself, and an oscillator ring stop signal. The latter is added as a concession to the software logic simulator programs used so that computer resources are not wasted simulating unnecessar...