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Nodal Impedance Test Generation System

IP.com Disclosure Number: IPCOM000088115D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Bauer, R: AUTHOR [+4]

Abstract

This test generation system utilizes the Numeric Control Restructured Engineering Interface File (N/C REIF) tape from which records 01, 10, 31 and 55 are compiled to define the net patterns of the raw card. These selected records are those that define the technology, voltages and card size, the wiring of the card, and the component placement. This net structure contains all the following required information for the performance of the raw card test: 1. Defines all wire by tape cross-reference and circuit net. 2. Defines the end points of each net. 3. Defines the number and value of the voltages in the net. 4. Defines each voltage pin. 5. Indicates the points in each net as a node or tab pin. 6. Indicates the plane that each wire within a net is on.

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Nodal Impedance Test Generation System

This test generation system utilizes the Numeric Control Restructured Engineering Interface File (N/C REIF) tape from which records 01, 10, 31 and 55 are compiled to define the net patterns of the raw card. These selected records are those that define the technology, voltages and card size, the wiring of the card, and the component placement. This net structure contains all the following required information for the performance of the raw card test: 1. Defines all wire by tape cross-reference and circuit net. 2. Defines the end points of each net. 3. Defines the number and value of the voltages in the net. 4. Defines each voltage pin. 5. Indicates the points in each net as a node or tab pin. 6. Indicates the plane that each wire within a net is on.

From this data, the NODXL Impedance Test application programmer can have the probe test pins automatically or manually assigned to the nets through an option in a control card. The option is also available to assign only one pin per net, no tab pins, no voltage pins, and to indicate the type of test required. The automatic assignment of pins is done through a "fixture rule" defined in the program. This rule describes the type of tester, number of test pins, and the pin configuration.

Based on the net data, the pin assignment and the options defined, the system will generate one of the following: 1. The shorts and/or continuity test for a circuit card assembly, complete with diagno...