Browse Prior Art Database

Programmable Priority for Cycle Steal

IP.com Disclosure Number: IPCOM000088121D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Duggan, CJ: AUTHOR

Abstract

Cycle steal is a data transfer technique in a computer system for transferring data between input/output (I/O) devices and storage. Cycle steal imposes less burden on the system than program-controlled data transfers. Hence, cycle steal is normally at a higher priority level than interrupt levels except for the interrupt level for handling error conditions.

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Programmable Priority for Cycle Steal

Cycle steal is a data transfer technique in a computer system for transferring data between input/output (I/O) devices and storage. Cycle steal imposes less burden on the system than program-controlled data transfers. Hence, cycle steal is normally at a higher priority level than interrupt levels except for the interrupt level for handling error conditions.

Some types of I/O devices cannot tolerate the time burden of program controlled data transfers and therefore are serviced by cycle steal, but may have data transfer service requirements which could permit devices serviced by interrupt to take priority. Priority is selectively yielded by having the I/O device attachment with cycle-steal capability monitor current interrupts and by program control relinquish priority to predetermined interrupt levels. As an enhancement, if an interrupt level given priority does not complete its task within a predetermined amount of time, priority reverts to the cycle-steal I/O device attachment. The predetermined period of time is also programmable.

In the computer system of Fig. 1, storage 10 contains instructions and data. Central processing unit (CPU) 15 fetches and executes instructions from storage 10 including instructions for controlling I/O data transfers. I/O device 25 is connected to CPU 15 via I/O device attachment 20, data bus in (DBI) 18 and data bus out (DBO) 19. I/O device 25 is connected on an interrupt level, and attachment 20 generates an interrupt request signal when I/O device 25 requires service. CPU 15 upon receiving the interrupt request signal will switch operations to the interrupt level for I/O device 25, if it happens to be the highest priority interrupt level requesting service.

I/O devices 35 and 36 are connected to the CPU via I/O controller 30, DBI 18 and DBO 19. I/O controller 30 is a microprogrammed controller, and I/O devices 35 and 36 are connected to be serviced by cycle-steal. Whenever I/O d...