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Control Sequencing using Programmed Logic Arrays

IP.com Disclosure Number: IPCOM000088124D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hicks, DR: AUTHOR

Abstract

Sequencers for controllers, microprogrammable data processors and similar devices frequently use conventional programmable logic array (PLA) circuits. In many cases, the number of output lines and the number of product terms for at least some of the output lines exceeds the resources of a single PLA integrated circuit. The conventional solution in such cases is to use a rectangular array 10 of individual PLA circuits 11 receiving address lines 12. The outputs of the PLAs in each column are "dot-OR'ed" to increase the number of available product terms. Additional columns increase the width of output bus 13.

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Control Sequencing using Programmed Logic Arrays

Sequencers for controllers, microprogrammable data processors and similar devices frequently use conventional programmable logic array (PLA) circuits. In many cases, the number of output lines and the number of product terms for at least some of the output lines exceeds the resources of a single PLA integrated circuit. The conventional solution in such cases is to use a rectangular array 10 of individual PLA circuits 11 receiving address lines 12. The outputs of the PLAs in each column are "dot-OR'ed" to increase the number of available product terms. Additional columns increase the width of output bus 13.

Part of the total width of bus 13 usually contains one or more fields which are needed only for a relatively small number of instructions, such as a literal field or an address field which is introduced into the data path only for certain instructions. One of the advantages of a PLA is that logical sequences need not be physically contiguous, e.g., instructions having operation codes 0000, 0001, 0011, etc., may be physically implemented as product terms 1, 28, 35, 17, etc., of one PLA, or may even be implemented on four different PLA chips. Given this characteristic, all of the instructions requiring, for example, the portion 14 of bus 13 may be implemented in the single PLA 15. This eliminates the requirement for several other PLAs, shown by the dashed blocks below PLA 15. Savings may be accomplished even when m...