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Different Data Rate Terminals on Same Loop

IP.com Disclosure Number: IPCOM000088130D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 80K

Publishing Venue

IBM

Related People

Calva, JR: AUTHOR

Abstract

In a communication system having synchronous data link control (SDLC), terminals with different data rates are attached to the same loop. This arrangement eliminates the need of separate loops, one loop for each set of terminals having the same data rate. It also removes the constraint of running all terminals at the data rate of the slowest terminal.

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Different Data Rate Terminals on Same Loop

In a communication system having synchronous data link control (SDLC), terminals with different data rates are attached to the same loop. This arrangement eliminates the need of separate loops, one loop for each set of terminals having the same data rate. It also removes the constraint of running all terminals at the data rate of the slowest terminal.

The primary station or loop controller at the host system creates a speed control character at the beginning of each operation cycle, where an operation cycle is defined as a speed control character followed by output frames (if required), followed by an optional response poll frame, followed by input frames (if available), followed by an idle period (if required). Operation cycles are logically equivalent at each data rate and in this instance one to four operation cycles may take place. The second, third and fourth cycles are logical duplicates of the first cycle but at data rate speeds of 1/2, 1/4 and 1/8 of the maximum data rate speed.

The primary station or loop controller maintains an idle period for secondary stations of the same data rate speed to switch loop station connector relays for connection onto the loop when their data rate cycle is active. If a secondary station is to disconnect, the primary station or loop controller provides an idle time for relay switching.

The speed control character is obtained by a one-bit insertion and deletion algorithm. A one bit is inserted by the transmitting local loop adapter (LLA) or secondary loop adapter (SLA) after the occurrence of five consecutive zero bits. If a one bit is received after five consecutive zero bits, the receiving LLA or SLA must delete the inserted one bit. Speed control character generation and detection is at the maximum data rate of the loop. Higher level logic, internal to the primary or secondary stations, experiences the absence of a bit timing clock signal when one bits are inserted or deleted. Transition of the bit timing clock signal to the active state is delayed until insertion or deletion is completed. The higher level logic on the SLA circuit card at secondary stations forces zero bits for all received data if the operation cycle is not for that secondary station, i.e., the speed control character detected by the secondary station indicates a data rate different than that of the secondary station. Received data, however, is passed to a terminal at the appropriate data rate when the current operation cycle is at a data rate which matches the data rate for that terminal. The SLA front-end logic at the transmit/receive circuits which decodes the transmitted speed control character...