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Running a Logic Circuit Simulator Until Stable

IP.com Disclosure Number: IPCOM000088143D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Beaven, PA: AUTHOR

Abstract

This article describes a technique for solving the problem of timing the sequences of input signals to a logic simulation model.

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Running a Logic Circuit Simulator Until Stable

This article describes a technique for solving the problem of timing the sequences of input signals to a logic simulation model.

A program, controlling the simulation of a logic circuit which has been modelled in software using a logic circuit simulator, applies a set of input signals (an input pattern) to the circuit at timed intervals T1, T2, T3 --- TN. The input pattern applied at T1 will generally change the circuit in some way, and as the simulated time progresses (in discrete steps), the circuit will eventually become stable. (Stability is defined as a state such that if the simulation run is continued without changing the input pattern no subsequent changes will occur in any part of the circuit.)

In order that the simulation can be run as fast as possible, then the next input pattern should be applied as soon as the circuit has stabilized after the previous pattern. Thus the time intervals between T1, T2, etc., will not necessarily be of the same duration.

Fig. 1 shows the situation diagrammatically where Delta Eta is the time needed to stabilize after the input applied at TN.

It is not practical to predict Delta Eta and then incorporate these values in the control program which sets up the simulator input patterns. Hence a conditional decision is introduced into the control program to monitor the stability of the circuit.

Fig. 2 is a flow chart that the controlling programs could have where the conditional st...