Browse Prior Art Database

High Speed Scanner Photoelement With Gain

IP.com Disclosure Number: IPCOM000088162D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Chamberlain, SG: AUTHOR

Abstract

In solid-state scanner applications high speed scanning is very desirable. With present solid-state scanners an increased integration speed corresponds to the reduction of the photoelement light integration time. In such case in order to maintain the original signal-to-noise ratio of the photoelement array, in practice, the scene illuminance is increased by increasing the wattage of the illuminator. Finally this process sets a limit to the maximum integration frequency of operation of the photo-element array.

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High Speed Scanner Photoelement With Gain

In solid-state scanner applications high speed scanning is very desirable. With present solid-state scanners an increased integration speed corresponds to the reduction of the photoelement light integration time. In such case in order to maintain the original signal-to-noise ratio of the photoelement array, in practice, the scene illuminance is increased by increasing the wattage of the illuminator. Finally this process sets a limit to the maximum integration frequency of operation of the photo-element array.

In addition, the output video rate of CCD (charge-coupled device), BBD (bucket brigade device) and FET (field-effect transistor) scanners is limited by the speed of the scanning shift registers associated with the photoelement array. In practice, one way to improve the scanning speed is to use multiplexing circuit techniques. The latter leads to increased scanner complexity.

This article describes a technique which provides solutions to the reduction of the integration time by a factor greater than 100, without loss of photosensitivity. Further, output video rates in excess of 100 MHz are anticipated with the described photoelement and scanning technique.

An n+ p n structure is used in association with an nIS gate whose potential well minimum occurs in the semiconductor bulk. This potential well acts as a collector for the n+ p n device and for the photogenerated carriers. The device is shown in Fig. 1A and its approximate equivalent circuit in Fig. 1B. In Fig. 1B the current I(1)is equal to I(ph1)(h(fe) +1), where h(fe) is the common emitter current gain of the transistor.

The n region is completely depleted with the aid of an external reverse bias. A voltage applied to the polysilicon gate X, which surrounds the n+ pn structure, will create a potential well minimum whose depth (Chi(m)) relative to the surface is given by: Chi(m) = (Epsilon si/(epsilon ox) . Tox (Cox/(CG)) -1. where Cox = oxide capacitance, CG = gate capacitance...