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Current Inverter for Josephson Memory Arrays

IP.com Disclosure Number: IPCOM000088167D
Original Publication Date: 1977-Apr-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Zappe, HH: AUTHOR

Abstract

A current inverter for Josephson memory arrays is disclosed in which the Josephson threshold current does not have to be entirely suppressed by a control field to obtain current inversion in the selection lines of a Josephson memory array. To circumvent the problem of special gate design which appears in known current inverters, the array loops through which current must flow in two directions must be decoupled by resistors so that current is transferred in a single superconducting loop. The dynamics of this transfer can be tailored to achieve small rest currents without requiring fully suppressed threshold current of an associated driver device.

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Current Inverter for Josephson Memory Arrays

A current inverter for Josephson memory arrays is disclosed in which the Josephson threshold current does not have to be entirely suppressed by a control field to obtain current inversion in the selection lines of a Josephson memory array. To circumvent the problem of special gate design which appears in known current inverters, the array loops through which current must flow in two directions must be decoupled by resistors so that current is transferred in a single superconducting loop. The dynamics of this transfer can be tailored to achieve small rest currents without requiring fully suppressed threshold current of an associated driver device.

An implementation of such a circuit is shown in the above figure. Each array loop 1 contains two drivers A,B fed by two resistors R. Array loops 1 are interconnected by interconnections 2.

Each loop 1 has serially disposed therein a plurality of memory cells 3 through which current must be passed in two directions.

Equal currents fed from a DC source initially flow upwardly through drivers A and B of the rightmost loop 1. The polarity of each of the array loop currents is determined by the last stage of an associated decoder which is shown electromagnetically coupled to the middle loop 1 of the above figure. If, for example, gate A is switched by the decoder, the current in that branch is diverted downward through the array loop through the serially disposed memory cell string...