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Browse Prior Art Database

Shift Register Verifier

IP.com Disclosure Number: IPCOM000088191D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Lutter, EP: AUTHOR

Abstract

Shift registers are used throughout data processing units as parallel-to-serial converters and for communication line drivers. In highly reliable units it is desired to inexpensively verify successful operation of a shift register. Verification is achieved by a double-bit check. A shift register (SR) checker receives signals from a shift register having a predetermined number of data stages. The last bit of the shift register is always preset to a logical one, signifying the end of the string of bits.

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Shift Register Verifier

Shift registers are used throughout data processing units as parallel-to-serial converters and for communication line drivers. In highly reliable units it is desired to inexpensively verify successful operation of a shift register. Verification is achieved by a double-bit check. A shift register (SR) checker receives signals from a shift register having a predetermined number of data stages. The last bit of the shift register is always preset to a logical one, signifying the end of the string of bits.

The SR checker counts the number of bits, and looks for a logical one in the last bit position. Then an additional shift of the shift register (an open-ended shift register) should produce a logical zero. The SR checker then checks for a logical zero following a logical one, i.e., checks for a logical zero in a phantom bit position of the shift register. The SR checker flags an error if the one-zero pattern does not always follow the normal data signal pattern. Upon completion of such shifting, the shift register contains all zeros. An all-zeros detector (not shown) can be added to the SR checker for verifying the shift-out operation.

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