Browse Prior Art Database

Programmable Architectural Array

IP.com Disclosure Number: IPCOM000088223D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Stoops, EH: AUTHOR

Abstract

In this array, individual logic circuits are enabled or disabled by a programmable control signal. As a result, different optional logic configurations are made possible to the user in the field.A

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Programmable Architectural Array

In this array, individual logic circuits are enabled or disabled by a programmable control signal. As a result, different optional logic configurations are made possible to the user in the field.A

Chip 1 contains a functional unit 2 of normal and optional functional circuits, e.g., ANDs and ORs. The support circuitry 3 decodes the input signals of input lines Ao - An in conjunction with feedback signals derived from the output signals of output lines Bo - Bn. In response thereto, it programs, via the programmable architectural array 4, the appropriate function control lines Co - Cn to either the complementary binary enable or disable state, utilizing a reference voltage, e.g., ground line 5. The pattern of enables and disables programmed on the function control lines Co - Cn determines the architecture, organization, or function of functional unit 2.

Chip 1 is thus capable of providing a wide variety of functional configurations without the necessity of dedicating the chip to a particular function and/or providing a different interconnector mask for each particular function.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]