Browse Prior Art Database

Multiphase System Clock

IP.com Disclosure Number: IPCOM000088224D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 71K

Publishing Venue

IBM

Related People

Firestine, GM: AUTHOR [+2]

Abstract

The arrangement shown in the block diagram is an implementation of a two-phase nonoverlapping digital clock system with multiple control modes. It is not limited to two phases, since it can be extended to multiple phases by adding more positions in the shift register contained in the system and/or replacing one of the trigger circuits with a counter and decoding the count therefrom to produce additional phases. Also, one controlling latch can be used to generate additional phases by controlling set and reset times. The arrangement basically comprises a crystal oscillator 3, the output of which is arranged to drive a shift register 5, the output of which is decoded by combinational decoding circuits 7, and the output therefrom fed back as a serial input to the shift register 5.

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Multiphase System Clock

The arrangement shown in the block diagram is an implementation of a two- phase nonoverlapping digital clock system with multiple control modes. It is not limited to two phases, since it can be extended to multiple phases by adding more positions in the shift register contained in the system and/or replacing one of the trigger circuits with a counter and decoding the count therefrom to produce additional phases. Also, one controlling latch can be used to generate additional phases by controlling set and reset times. The arrangement basically comprises a crystal oscillator 3, the output of which is arranged to drive a shift register 5, the output of which is decoded by combinational decoding circuits 7, and the output therefrom fed back as a serial input to the shift register 5. The output of 7 is also supplied to the input of a first trigger 9, connected in toggle fashion so that the outputs of trigger 9 are alternated in response to the inputs therefrom from 7. The outputs of the trigger 9 are supplied as inputs to first and second AND circuits 11 and 13, the negative outputs therefrom constituting the two negative phase outputs of the clock system designated as -B2 and -B1, respectively.

A latch configuration, comprising OR circuit 15, AND circuit 17 and inverter 19, is used to enable the output AND circuits 11 and 13 during the time that the shift register 5 is shifting from its first output condition to its final output condition.

A second trigger circuit 21 is used as a single-shot device to provide a single cycle advance feature for this configuration. The additional logic circuits are involved in controlling the various modes of the system, as will be described below.

The present arrangement contains provisions for a single cycle operation and other stopping modes in addition to the normal or continuous run mode. It also provides that a full pulse-width phase cycle is always presented to the logic in that at the initial start-up time the first phase is always present. The continuous mode control line 23, when active, allows the clock to run by supplying a signal through OR circuit 25 to one input of AND circuit 27 at the serial input for shift register 5. The other input to AND circuit 27 is the output of a decoding circuit 7. When the continuous mode control line drops or goes negative, the clock interrupts the current phase output, and since the serial input of the shift register is degated at AND g...