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Semiconductor Substrate EPI Layer Evaluation Process

IP.com Disclosure Number: IPCOM000088228D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Beyer, KD: AUTHOR [+3]

Abstract

The interaction of substrate and epi (epitaxial) layer defects can be evaluated by a delineation method. This method can be applied to measurements such as Zerbst analysis, Schottky barrier diode measurements, scanned surface voltage and anodic etch technique.

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Semiconductor Substrate EPI Layer Evaluation Process

The interaction of substrate and epi (epitaxial) layer defects can be evaluated by a delineation method. This method can be applied to measurements such as Zerbst analysis, Schottky barrier diode measurements, scanned surface voltage and anodic etch technique.

Aluminum dots are deposited on a thermally grown SiO(2) layer 1 on silicon substrate 2, and MOS and scanned surface voltage measurements are taken. Then oxide layer 1 is completely removed outside of the aluminum dots by HF/H(2)O vapor etching. The aluminum is then removed with a H(3)PO(4)/HNO(3)/H(2)O solution. Silicon step 3 is then introduced by a preferential silicon etch (.7 ml HF in 100 ml HNO(3)). The remainder of layer 1 is then removed by HF/H(2)O vapor etching and an epi layer is deposited over the silicon. Step 3 remains visible.

Tests such as etch pit studies, Schottky barrier diode tests and/or anodic etch tests can be performed on all dot locations which have been initially evaluated prior to any heat treatment and epitaxial deposition. Also, after an oxide growth, MOS data can be obtained. The method permits evaluation of wafer preparation treatments such as external or internal gettering and cleaning processes with respect to their impact on epitaxial quality by assuring the testing of the same wafer (dot) locations before and after treatment.

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