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Method for Reducing the Emitter Base Contact Distance in Bipolar Transistors

IP.com Disclosure Number: IPCOM000088239D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

The performance of integrated circuits incorporating bipolar transistors is known to be sensitive to the spacing between the emitter and base. This spacing is determined by existing semiconductor processing including photolithography and film etching, which requires a minimum of 2 mu m overlap of metal over an edge of a contact and a minimum of 2.5 mu m spacing between adjacent metal lines. As a specific illustration, the sensitivity of the circuit delay of an emitter-coupled logic (ECL) gate at various power levels, as computed through ASTAP-aided circuit simulation, has been shown.

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Method for Reducing the Emitter Base Contact Distance in Bipolar Transistors

The performance of integrated circuits incorporating bipolar transistors is known to be sensitive to the spacing between the emitter and base. This spacing is determined by existing semiconductor processing including photolithography and film etching, which requires a minimum of 2 mu m overlap of metal over an edge of a contact and a minimum of 2.5 mu m spacing between adjacent metal lines. As a specific illustration, the sensitivity of the circuit delay of an emitter- coupled logic (ECL) gate at various power levels, as computed through ASTAP- aided circuit simulation, has been shown.

A method of fabricating bipolar transistors, together with the usual resistors and Schottky diodes, is presented below. This method allows the emitter-base contact spacing to be designed as small as 2.5 mu m while using existing processing techniques up to emitter diffusion. The emitter drive-in heat cycle is to be slightly reduced by the amount needed to grow about 2000 Angstrom thermal SiO(2). The cross-section of the processed wafer at this stage of fabrication is shown in Fig. 1, wherein the subcollector 10, recessed silicon dioxide 12, P junction subisolation 14, base region 16, emitter region 18, thermal silicon dioxide 19, silicon nitride layer 20 and pyrolytic silicon dioxide layer 22 are its structural elements. The subsequent steps of fabrication are as follows: (a) Deposit about 7000 Angstroms thick N+ doped polysilicon 24. (b) Through photolithography, etch patterns in polysilicon. (c) Grow about 2000 Angstroms thermal SiO(2) 26 over polysilicon. (d) Through photoresist mask, etch SiO(2) selectively. (e) Deposit about 1 mu m thick aluminum 28 and etch patterns in the metal to produce the structure of Figs. 2 and 3.

In the above embodiment, N+ doped polysilicon was shown to link the emitter and collector reach-through to metallization. While at low emitter and collector current level operation of the transistors, the ohmic drop across the polysilicon links may be acceptable, it would, in general, be preferable to introduce instead P+ doped polysilicon for linking the base-to-base metallization and retain metal for direct contacts to emitter and collector reach-through....