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Complementary Driver for Emitter Coupled Logic Gates

IP.com Disclosure Number: IPCOM000088244D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Chang, AW: AUTHOR [+3]

Abstract

Conventional emitter-coupled-logic (ECL) gates employ emitter followers with load resistors. Heavy power is consumed both in the "main switch" and its "output drivers". The circuit of the drawing uses local complementary signals to discharge the output line capacitances which are charged up by signals with opposite polarities.

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Complementary Driver for Emitter Coupled Logic Gates

Conventional emitter-coupled-logic (ECL) gates employ emitter followers with load resistors. Heavy power is consumed both in the "main switch" and its "output drivers". The circuit of the drawing uses local complementary signals to discharge the output line capacitances which are charged up by signals with opposite polarities.

Devices R1, R2, R3, T1 and T2 form the basic ECL gate. T3 and T7 are the emitter-follower transistors which charge up the line capacitances at both outputs. At down-swing, the lines will now see the saturation-driven transistors T5 and T8 instead of seeing the resistor legs formed by R6 and R7 or R4 and R5. Very high speed output down-driving is achievable with relatively low power. The bases of T5 or T8 are served via T6 or T4 by the signals at points F or E, respectively.

T9 and D1, D2 are clamping diodes for nodes E and F. With these devices, collector dotting of other ECL gates is allowed. D3 and D4 are the integrated Schottky diodes for T5 and T8, respectively. The whole circuit now represents a logic gate with "active" up-and-down driving capabilities. The power-speed product is much less than the "active upswing and passive down-swing" conventional circuit. It is to be noted that this is achieved by conventional NPN transistor technology.

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