Browse Prior Art Database

MTL to TTL Interface Circuit

IP.com Disclosure Number: IPCOM000088254D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Lebesnerais, G: AUTHOR [+2]

Abstract

The above interface circuit assures the conversion between the merged transistor logic (MTL) voltage levels (0 and 0.7V) provided by an MTL circuit such as transistor T1 and the transistor-transistor logic (TTL) levels (0 and O.5V).

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MTL to TTL Interface Circuit

The above interface circuit assures the conversion between the merged transistor logic (MTL) voltage levels (0 and 0.7V) provided by an MTL circuit such as transistor T1 and the transistor-transistor logic (TTL) levels (0 and O.5V).

It comprises an MTL reference circuit T2, the injection current Io of which is approximately mirrored in the collector of T3 and the collector of T4. The collector current of T4 is derived either in the collector of T1 (if T1 is on) or in the base of a standard large gain NPN transistor T5 (if T1 is off) which, according to the state of T2, provides the desired voltage level on its output terminal after adjusting resistor R to an appropriate value. Transistor T6 provides correct bias for the bases of transistors T3 and T4.

An advantage of this circuit lies in that it allows changes in the injection currents Io without any operating problems.

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