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Slew Rate Improving Circuit for a Voltage Comparator

IP.com Disclosure Number: IPCOM000088255D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Maillet, JC: AUTHOR

Abstract

In a voltage comparator comprising a first differential amplifier T1, T2 with emitter coupling current source T3, the switching speed is limited by the parasitic capacitor Cp (shown in dashed lines) associated with each transistor.

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Slew Rate Improving Circuit for a Voltage Comparator

In a voltage comparator comprising a first differential amplifier T1, T2 with emitter coupling current source T3, the switching speed is limited by the parasitic capacitor Cp (shown in dashed lines) associated with each transistor.

When a large negative voltage transition is applied to an input 1, the other input 2 being grounded, voltage at node X cannot follow because of the discharge speed of capacitor Cp through transistor T3. The discharge speed depends on the current which would have to be increased to improve the slew rate of the comparator.

Circuit 3 performs this function by increasing the emitter current of the differential amplifier transistors T1 and T2 when a negative voltage transition is applied to one input, since it is this transition which creates the input slew rate phenomenon. For positive input transition, the emitter current will stay unchanged.

By means of this circuit, the working emitter current of the input differential stage is the sum of currents IB and IS performed in transistor T3. The IB current, which is the quiescent current of the input stage, is supplied by transistor T8. The IS current, which is supplied by the differential arrangement of transistors T4 and T5, is the supplementary transient current which increases the input slew rate when a negative voltage transition is applied to the input.

The bases of the transistor T4 and T5 are biased by the voltage drop across resisto...