Browse Prior Art Database

Instruction Buffer Loading

IP.com Disclosure Number: IPCOM000088260D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Bazlen, D: AUTHOR [+9]

Abstract

The instruction buffer stores 16 bytes (8 half-words) which are loaded, via a 4-byte bus, from main store (MS) into the buffer in four consecutive transfer operations. The respective buffer half-word address is generated and set into buffer address register (BAR) by a modifier that also loads the MS address register (SAR).

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Instruction Buffer Loading

The instruction buffer stores 16 bytes (8 half-words) which are loaded, via a 4-byte bus, from main store (MS) into the buffer in four consecutive transfer operations. The respective buffer half-word address is generated and set into buffer address register (BAR) by a modifier that also loads the MS address register (SAR).

When the buffer has to be reloaded at a given half-word address, this address incremented by 4 mod 16, together with the high order address bytes from local store, is set in the SAR. In the buffer, reloading also starts with this address incremented by 4 mod 16 and proceeds cyclically through the 16 bytes.

After the four full-words have been loaded into the buffer, the BAR again stores the original half-word address, and the instruction half-word at this address can be immediately read out, without any additional address modification or buffer-access operation being required.

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