Browse Prior Art Database

Polarity Hold Integrator

IP.com Disclosure Number: IPCOM000088269D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Aaron, RT: AUTHOR

Abstract

This circuit integrates an input and then latches the integrated signal.

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Polarity Hold Integrator

This circuit integrates an input and then latches the integrated signal.

With the HOLD signal up, the input signal is integrated by the combination of transistor Q1 and capacitor C. The integrated output is provided at the drain of device Q2. The integrated output is latched when the H0LD signal comes up and remains that way until the HOLD signal goes down. Then, the circuit is ready to receive another input signal.

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