Browse Prior Art Database

Static Logic Layout Concept

IP.com Disclosure Number: IPCOM000088271D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hadamard, G: AUTHOR

Abstract

A static field-effect transistor (FET) logic layout is disclosed which embeds a NOR cell in a grounded diffusion blanket. The source of the active devices is the grounded diffusion blanket. The drain of the active devices and the loads are in cells embedded in the blanket diffusion. This results in a reduced metal capacitance and improved packing density.

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Static Logic Layout Concept

A static field-effect transistor (FET) logic layout is disclosed which embeds a NOR cell in a grounded diffusion blanket. The source of the active devices is the grounded diffusion blanket. The drain of the active devices and the loads are in cells embedded in the blanket diffusion. This results in a reduced metal capacitance and improved packing density.

The layout in Fig. 1 is for the delayed flip-flop trigger shown in Fig. 2. The source of the active devices, which have to be grounded, is actually made with a blanket of grounded diffusion 10. The drains of these active devices, and the loads are in cell 12 embedded in the blanket diffusion 10. V+ is distributed by metal lines 14 in the middle of the cell. Underpass 16, needed, for instance, to cross the V+ wires 14, is also embedded in the grounded blanket diffusion 10.

The advantages of the layout include the following: Since the grounded diffusion 10 surrounds the active gates, the diffusion resistance is reduced. Since the celL does not extend farther from one bus bar than from the other, the density is increased. Since metal wiring will now primarily run over the diffusion instead of the P substrate, the capacitance of this wiring will decrease because oxide thickness, is 10,000 angstroms over the diffusion blanket 10 and 7,000 angstroms over the substrate. The design employs a trapezoidal gate shape for both FET active and load devices.

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