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In Phase Weak Signal Input Circuit

IP.com Disclosure Number: IPCOM000088273D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Love, RD: AUTHOR

Abstract

A field-effect transistor (FET) static current circuit is disclosed which provides an in-phase amplification of a weak binary signal. The figure shows three inverter stages, the first stage comprising FETs 5 and 6 the second stage comprising FETs 1 and 2, and the third stage comprising FETs 3 and 4, with FETs 1, 3 and 5 being depletion-mode devices and FETs 2, 4 and 6 being enhancement-mode devices.

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In Phase Weak Signal Input Circuit

A field-effect transistor (FET) static current circuit is disclosed which provides an in-phase amplification of a weak binary signal. The figure shows three inverter stages, the first stage comprising FETs 5 and 6 the second stage comprising FETs 1 and 2, and the third stage comprising FETs 3 and 4, with FETs 1, 3 and 5 being depletion-mode devices and FETs 2, 4 and 6 being enhancement-mode devices.

In the first stage, FET 5 is connected as a saturated load with its gate connected to its source at node B, and FET 6 is the input device with its gate connected to the input node A. In the second stage, FET 1 has its gate connected to the input node A, and FET 2 has its gate connected to node B of stage 1. The combination of the first and second stages constitutes a push-pull true circuit with a positive polarity pulse on the input node A generating a positive polarity pulse on node C which connects the source of FET 1 and the drain of FET 2. In the third stage, the gate of FET 3 is connected to node C of stage 2, and the gate of FET 4 is connected to node B of stage 1. A third stage inverter consitutes a push-pull output stage for the push-pull true circuit constituting devices 1, 2, 5 and 6. The output node D which connects the source of device 3 to the drain of device 4, outputs an amplified positive-going signal when the positive-going weak signal is at the input node A.

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