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Storage To Storage Variable Length, Signed Binary Instructions

IP.com Disclosure Number: IPCOM000088299D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 8 page(s) / 119K

Publishing Venue

IBM

Related People

Bains, RL: AUTHOR [+5]

Abstract

Instructions Add Character (AC), Subtract Character (SC), Compare Character (CC) and Zero and Add Character (ZAC) directly operate on variable length, signed binary storage operands. These instructions simplify code generation for signed binary data in storage because the operands can be of any length up to a predetermined maximum and need not be loaded into registers for processing. There is also a reduction in the amount of main storage instruction space required for the function to be performed because a single instruction replaces several instructions. This, of course, increases performance because only a single instruction fetch is required. Operands 1 (OP 1) and 2 (OP 2) have individual lengths, and this allows OP 1 to be less than, greater than or equal to OP 2.

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Storage To Storage Variable Length, Signed Binary Instructions

Instructions Add Character (AC), Subtract Character (SC), Compare Character (CC) and Zero and Add Character (ZAC) directly operate on variable length, signed binary storage operands. These instructions simplify code generation for signed binary data in storage because the operands can be of any length up to a predetermined maximum and need not be loaded into registers for processing. There is also a reduction in the amount of main storage instruction space required for the function to be performed because a single instruction replaces several instructions. This, of course, increases performance because only a single instruction fetch is required. Operands 1 (OP 1) and 2 (OP 2) have individual lengths, and this allows OP 1 to be less than, greater than or equal to OP 2. Hence, mixed length calculations require no special processing.

The AC, SC, CC and ZAC instructions are contained in Main Storage 1 (Fig.
1). The AC instruction has the following format:

During execution of the AC instruction, the second operand is added to the first operand and the sum is placed in the first-operand location. The addition is performed with both operands treated as signed binary quantities. If the carry out of the sign-bit position and the carry out of the leftmost numeric bit position agree, the sum is satisfactory; if they disagree, an overflow occurs. The sign bit is not changed after the overflow. A positive overflow yields a negative final sum, and a negative overflow results in a positive sum.

The L1 and L2 fields in the instruction specify one less than the number of bytes for each operand. If the operands are unequal in length, the shorter operand is considered to be extended to the left with bits equal to the sign bit. If the first operand is too short to contain all significant bits of the result, an overflow occurs and the significant bits are lost. The operands may overlap in storage if the rightmost byte of the first operand is coincident with, or to the right of, the rightmost byte of the second operand; otherwise, the overlap is destructive. Resulting Condition Code: 0 Sum is zero 1 Sum is less than zero 2 Sum is greater than zero 3 -- Program Exceptions: Access Binary Overflow

The SC instruction is similar to the AC instruction, except that it has a different OP code.

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During execution of the SC instruction, the second operand is subtracted from the first operand and the difference is placed in the first-operand location. The operands are treated as signed binary quantities. Subtraction is performed as if the one's complement of the second operand and a rightmost one bit was added to the first operand. If the carry out of the sign-bit position and the carry out of the high-order numeric-bit position agree, the difference is satisfactory; if they disagree, an overflow occurs.

As in the AC instruction, the L1 and L2 fields in the instruction specify one less...