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Loop Drive Decoder Technique for Josephson Memory Arrays

IP.com Disclosure Number: IPCOM000088322D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Kotyczka, W: AUTHOR

Abstract

In the interleaved tree decoder proposed in the IBM Technical Disclosure Bulletin, Vol. 18, No. 12, May 1976, page 4168, much space is consumed by the complicated lines of the tree network. The loop decoder depicted here uses a method of simplified addressing of the drive junction. Several drive junctions use the same control line, thereby saving space and requiring fewer junction contacts. The matrix lines are served by drive-loops. Several drive-loops are grouped together into sub-loops. A sub-loop is selected from logic circuits by a first control line loop. A drive-loop is then selected within the sub-loop by a second control line loop. The second control line loop acts upon two junctions. Since the two junctions are in series in one drive-loop, the cycle-time of the array is reduced.

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Loop Drive Decoder Technique for Josephson Memory Arrays

In the interleaved tree decoder proposed in the IBM Technical Disclosure Bulletin, Vol. 18, No. 12, May 1976, page 4168, much space is consumed by the complicated lines of the tree network. The loop decoder depicted here uses a method of simplified addressing of the drive junction. Several drive junctions use the same control line, thereby saving space and requiring fewer junction contacts. The matrix lines are served by drive-loops. Several drive-loops are grouped together into sub-loops. A sub-loop is selected from logic circuits by a first control line loop. A drive-loop is then selected within the sub-loop by a second control line loop. The second control line loop acts upon two junctions. Since the two junctions are in series in one drive-loop, the cycle-time of the array is reduced.

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