Browse Prior Art Database

System for Encoding Digital Data

IP.com Disclosure Number: IPCOM000088327D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Lee, RC: AUTHOR

Abstract

A system for encoding digital data to be recorded by a two-track magnetic tape system, where low cost is important, operates by encoding pulses at half the data transfer rate' The pulses are recorded on one track of the tape when `1's are found in the input data and on the other track when `0's are found. A simple encoder is shown in Fig. 1, and timing waveforms of the signals at various points of the encoder are shown in Fig. 2. The main components of the encoder are two JK flip-flops 1 and 2, which supply the record pulses to the two channels A and B, respectively, of the tape system.

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System for Encoding Digital Data

A system for encoding digital data to be recorded by a two-track magnetic tape system, where low cost is important, operates by encoding pulses at half the data transfer rate' The pulses are recorded on one track of the tape when `1's are found in the input data and on the other track when `0's are found. A simple encoder is shown in Fig. 1, and timing waveforms of the signals at various points of the encoder are shown in Fig. 2. The main components of the encoder are two JK flip-flops 1 and 2, which supply the record pulses to the two channels A and B, respectively, of the tape system.

In order to allow data to be read at an unknown speed, a marker is recorded before each data group simultaneously on both tracks of the tape.

A mark pulse is supplied on input line 3 and passed simultaneously to the J inputs of flip-flops 1 and 2. Since the K inputs of these two flip-flops are permanently held at a DC level representing a `1' state, a mark pulse M is produced on channel A and channel B from the Q output of the two flip-flops on occurrence of the trailing edge of the next clock pulse and is terminated by the trailing edge of the following clock pulse. A gate pulse is then supplied on input line 4 to condition a data ONE gate 5 to pass binary ONE bits of data on input line 6 to the J input of flip-flop 1 and to condition a data ZERO gate 7 to pass binary ZERO bits of data, inverted by inverter 8, to the J input of flip-flop 2.

The tw...