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Fault Simulation of Arrays and Macros with a Deductive Fault Simulator

IP.com Disclosure Number: IPCOM000088340D
Original Publication Date: 1977-May-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Donath, WE: AUTHOR [+3]

Abstract

In the deductive simulator described in the IBM Technical Disclosure Bulletin Vol. 19, No. 6, November 1976, pp. 2352-2353, each gate carries along with it a fault list; each fault on this list would invert the output value of that gate. The present article describes a scheme to impact both core requirement and computation time by reducing fault list size for the gates internal to combinational macros by fault simulating these with reduced fault lists. When a macro is to be simulated, assume that the values and fault lists on all its input signals are defined. These faults are then divided into "equivalence classes" on the basis of the inputs each fault appears on.

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Fault Simulation of Arrays and Macros with a Deductive Fault Simulator

In the deductive simulator described in the IBM Technical Disclosure Bulletin Vol. 19, No. 6, November 1976, pp. 2352-2353, each gate carries along with it a fault list; each fault on this list would invert the output value of that gate. The present article describes a scheme to impact both core requirement and computation time by reducing fault list size for the gates internal to combinational macros by fault simulating these with reduced fault lists. When a macro is to be simulated, assume that the values and fault lists on all its input signals are defined. These faults are then divided into "equivalence classes" on the basis of the inputs each fault appears on. For example, a fault that appears on inputs "a" and "b" of a macro is considered equivalent to any other fault that appears on just these two inputs, but faults which appear on inputs "a" only or on inputs "a", "b" and "c" belong to a different equivalence class. One representative of each class is used for the simulation to the output gates of the macro. Since all faults belonging to the same equivalence class behave alike, the fault lists on the outputs can be reconstituted from the representatives. Faults internal to the macro can be simulated along with the faults on its inputs.

A hierarchical scheme can readily be implemented; macros inside macros can be handled according to the same scheme.

It is to be noted that no separate area is needed for macro simulation, even though one could be provided. It is also possible to erase information residing on gates internal to macros after simulation for that macro is completed.

For macros with large numbers of inputs, a hash coding scheme would be advantageous for fault classification. For macros with small numbers of inputs, the hash coding scheme degenerates into a list classification scheme.

It is possible to implement a single-fault propagation scheme for some macros, so that a minimum of storage area is used for the behavior of a macro.

Mechanisms for recognizing a macro and simulating it only when all inputs are arranged must also be provided. This can be done by having the macro stored separately (when it is best to do single-fault propagation) of in-line with the other logic. Example:

During a logic simulation, a 10-circuit macro was observed with the functional behavior 01 = (a v b v c) ^ (a v e v f) ^ (d v b v f) ^ (d v e v c) 02 = (d v e v f) ^ (d...