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Accurate Proportional Variable Stress Testing Hardware Logic Design using Software Simulation

IP.com Disclosure Number: IPCOM000088353D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 26K

Publishing Venue

IBM

Related People

Ames, RN: AUTHOR [+2]

Abstract

A practical method is described for accurately stress testing hardware logic design in software simulation beyond what can be done by current methods or what can be done in actual hardware, to prevent over-design, over-simulation, and to improve products. The method features a Floating Point Processor detail logic representation driven by a Hi-level System Design Language (SDL) model of a Processor all in software Variable Mesh Simulation (VMS), and proportional variability of inputs to a fixed nominal delay logic representation to achieve accurate worst-case stress testing.

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Accurate Proportional Variable Stress Testing Hardware Logic Design using Software Simulation

A practical method is described for accurately stress testing hardware logic design in software simulation beyond what can be done by current methods or what can be done in actual hardware, to prevent over-design, over-simulation, and to improve products. The method features a Floating Point Processor detail logic representation driven by a Hi-level System Design Language (SDL) model of a Processor all in software Variable Mesh Simulation (VMS), and proportional variability of inputs to a fixed nominal delay logic representation to achieve accurate worst-case stress testing.

A representative hardware-oriented system includes central processing unit (CPU) 1 with associated channel 2, storage 3 and interconnected by bus 4 with a Floating Point Processor 5.

The Floating Point Processor circuits include two major adders, various registers and associated logic. One adder is for the Exponent which is a bit adder, and one adder for the fraction which is identified as a Carry Save Adder (CSA). The basic data flow comes from a random-access memory in the Floating Point Processor which is a stack of four registers per level, four levels. The floating point operand then is gated both to the Exponent adder and through the intermediate registers and into the Carry Save Adder where the arithmetic is accomplished. After the arithmetic is finished, the operands are gated back through the bus network to the random-access memory or to the I/O bus to Channel 2. Operands can come either from the random-access memory or a single operand can also come from the I/O bus from the Processor 1.

Prior to building the actual hardware depicted in the figure, the physical and loading characteristics are unknown. The simulation delay calculation makes assumptions to cover the most general delays expected. Delay simulation inaccuracy is caused by loading, packaging, wire length, circuit environment, and other assumptions that are not input to the program. Unique circuit delay rules that cannot be taken into account by a simulation delay estimator also contribute to the pessimistic delays generated by the simulation delay estimator. Delays may be calculated more accurately by using the selected circuit manual when the physical and loading parameters are known.

The use of software simulation to determine proper logic operation can be done with several types of delays specified for the logic blocks. Unit delay, nominal delay, 3 sigma slow, or 3 sigma fast delays may be specified to the delay simulator. If the delays are not accurate, then the results tend to be more optimistic or more pessimistic than the actual hardware delays. In some circuit technologies, for example, simulation delays tend to be slowe...